Recently, a liquid crystal display device (LCD), featured by thin thickness, lightness of weight and low power consumption, has become popular as a display device, and is now in use for a display device of a mobile information terminal device, such as a portable telephone set (mobile phone or cellular phone), PDA (personal digital assistant) or a notebook PC.
However, the technique for enlarging the size of the liquid crystal display device or for coping with moving pictures has advanced such that not only the LCD for mobile use but also the stationary type large screen display device or a large screen liquid crystal television receiver has become a reality. As the liquid crystal display device, a liquid crystal device of an active matrix driving system, providing for high definition display, is currently in use.
Referring first to FIG. 26, a typical configuration of the liquid crystal display device of the active matrix driving system is explained. In FIG. 26, the major configuration of the connected to a pixel of a liquid crystal display unit is schematically shown by an equivalent circuit.
In general, a display unit 960 of a liquid crystal display device of the active matrix driving system is made up by a semiconductor substrate, including a matrix array of transparent pixel electrodes 964 and thin-film transistors (TFTs) 963, a counter-substrate having a transparent electrode 966 on the entire surface, and a liquid crystal sealed in-between the two substrates. The semiconductor substrate includes the matrix array of 1280×3 columns of pixels by 1024 rows of pixels in the case of a color SXGA panel, as an example.
The TFT 963, having the switching function, has its on/off controlled by the scanning signal, such that, when the TFT 963 is turned on, the grayscale voltage corresponding to a picture signal is applied to the pixel electrode 964, and the liquid crystal has its transmittance changed by the potential difference across the pixel electrodes 964 and the electrode of the counter-substrate 966. This potential difference is maintained by a liquid crystal capacitance 965 for a preset time to display a picture.
On the semiconductor substrate, there is formed a lattice-like interconnection of data lines 962 for sending a plural number of level voltages (grayscale voltages) applied to the pixel electrodes 964, and scanning lines 961 for sending scanning signals. In the case of the color SXGA panel, 1280×3 data lines by 1024 scanning lines are formed on the semiconductor substrate. The scanning lines 961 and the data lines 962 represent a large capacitive load by e.g. the capacitance generated at the intersections and the liquid crystal capacitances sandwiched across the electrodes of the two substrates.
Meanwhile, the scanning signals are supplied from a gate driver 970 to a scanning line 961, whilst the grayscale voltage to the respective pixel electrodes 964 is supplied over a data line 962 by a data driver 980.
Data for one frame is rewritten every frame period ( 1/60 second) and is selected with each scanning line from one row of pixels to the next (every line). The grayscale voltage is supplied from each data line.
It is sufficient for the gate driver 970 to supply at least two-valued scanning signals, while the data driver 980 is required to drive the data lines with the grayscale voltages of multi-valued levels corresponding to the number of grayscales. Thus, a differential amplifier capable of outputting the voltage to high precision is used as a buffer unit of the data driver 980.
Moreover, the recent tendency is to raise the picture quality (multicolor quality) in the liquid crystal display device, such that there is an increasing demand for at least 2,600,000 colors, corresponding to 6-bit image data for each of R, G and B, and even as many as 26,800,000 colors, corresponding to 8-bit image data for each of R, G and B.
For this reason, a voltage output to an extremely high accuracy is required of the driver, outputting the grayscale voltage corresponding to multi-bit image data. In addition, the number of devices in a circuit unit for processing image data is increased and hence the chip area of the data driver LSI is increased, thereby raising the cost. This problem is discussed in detail hereinbelow.
FIG. 27 shows the configuration of the data driver 980 of FIG. 26. Referring to FIG. 27, the data driver 980 is made up by a latch address selector 981, a latch 982, a grayscale voltage generating circuit 983, a plural number of decoders 984, and a plural number of buffer circuits 985.
The latch address selector 981 determines the data latch timing based on a clock signal CLK.
The latch 982 latches video digital data signals, based on a timing, as determined by the latch address selector 981, and output data signals to the respective decoders 984 at a time, responsive to a STB (strobe signal).
The grayscale voltage generating circuit 983 generates a number of grayscale voltages, which stand for a number of grayscales corresponding to input data.
The decoder 984 selects one grayscale voltage, corresponding to the input data, to output the so selected grayscale voltage.
The buffer circuit 985 is supplied with the grayscale voltage, output from the decoder 984, which is then subjected to current amplification and output as an output voltage Vout.
For example, in case 6-bit video data is supplied, the number of the grayscales is 64, and the grayscale voltage generating circuit 983 generates 64 levels of the grayscale voltages. The decoder 984 is configured for selecting one of the 64-level grayscale voltages.
On the other hand, in case 8-bit image data is input, the number of grayscales is 256. The grayscale voltage generating circuit 983 generates 256 levels of the grayscale voltages. The decoder 984 is configured for selecting one of the 256-level grayscale voltages.
If the video data is multi-bit data, in this manner, the grayscale voltage generating circuit 983 and the decoder 984 are increased in circuit size. For example, if the video data is increased from e.g. 6 bits to 8 bits, the circuit size is increased by a factor not less than four. Hence, as the video data becomes multi-bit data, the chip area of the data driver LSI is increased to raise the cost.
In contradistinction to the foregoing, such a configuration which will minimize the increase in the chip area of the data driver LSI, even though the video data becomes multi-bit data, has been proposed in the Patent Document1 or in the Patent Document2, recited hereinbelow. FIG. 28 shows an example of the configuration proposed in the Patent Document1.
Referring to FIG. 28, the data driver differs from that shown in FIG. 27 in the configuration of a grayscale voltage generating circuit 986, a decoder 987 and a buffer circuit 988.
With the grayscale voltage generating circuit 986 of FIG. 27, the grayscale voltages are generated every two grayscales to decrease the number of grayscale voltage lines of the decoder 987 to approximately one-half of the number of the decoders 984 of FIG. 28.
The decoder 987 is responsive to the video data to select two grayscale voltages to output the selected grayscale voltages to the buffer circuit 988. The buffer circuit 988 is able to current-amplify the input two grayscale voltages and a grayscale voltage intermediate between the two grayscale voltages to output the resulting voltages.
With the configuration, shown in the Patent Documents 1 and 2, provided with the buffer circuits 988, each designed to be supplied with the two grayscale voltages to output one of the two grayscale voltages and the intermediate voltage, the number of the grayscale voltage lines of the decoder 987 may be halved in order to reduce the circuit scale of the decoders 987 to save the area and hence the production cost. It is therefore possible to suppress the increase in the chip area of the data driver LSI against the increase in the number of bits of the video data signals.
As a differential amplifier for the buffer circuits 988, a configuration shown in FIG. 5B of the Patent Document 1, or a configuration shown in FIG. 15 of the Patent Document 2, has been proposed. The configuration shown in FIG. 5B of the Patent Document 1, in which an output of the differential pair is an input end of a current mirror, which is arranged in a diode-connection, is thought not to operate as a differential amplifier.
However, from FIG. 15 of the Patent Document 2, relevant to the Patent Document 1, the illustrative features of the differential amplifier, proposed in the Patent Documents 1 and 2, presumably reside in those of the differential amplifier, having a differential state 910, as shown in FIG. 29.
FIG. 29 shows the configuration of a two-input differential amplifier. A differential stage 910 is featured by transistors 903 and 904 of a second differential pair being connected parallel to transistors 901 and 902 of a first differential pair, with the two differential pairs being driven by a common current source 907. The gates of the transistors 901 and 903 are supplied with grayscale voltages Vp1 and Vp2, respectively, while the gates of the transistors 902 and 904 are connected in common and supplied with an output Vn1 of the differential amplifier in a feedback fashion. Output pairs of the first and second differential pairs are connected to input and output ends of the current mirror circuit (905, 906), to perform an amplifying operation conforming to a common output signal of the first and second differential pairs.
In the above-described configuration of the differential amplifier, the output voltage Vn1 is equal to the input voltage when the voltages Vp1 and Vp2 are the same input voltage and, when the voltages Vp1 and Vp2 differ from each other, the output voltage Vn1 is intermediate between the voltages Vp1 and Vp2.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-2001-34234 (FIGS. 5, 20, 21)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-2001-343948 (FIG. 15)